The present invention relates to a wafer provided with solder bumps for use in flip-chip bonded integrated circuits where a metallic xe2x80x9ccapxe2x80x9d over the under bump metal is used as a barrier layer.
In the manufacture of integrated circuits it is known to attach a semiconductor chip to a substrate through a plurality of solder bump interconnections which are first formed on the integrated circuit and which is subsequently assembled face down on the substrate. As well as providing electrical contacts the solder bumps form mechanical and thermal connection between the chip and substrate. Solder compositions are usually based on tin alloys, and the most common is lead-tin.
The solder bumps are usually applied onto a series of intermediate metallic layers. More particularly, the semiconductor wafer includes metallic pads typically of aluminium over which are applied thin intermediate chromium and copper layers, and onto which is applied by electroplating a relatively thick layer of copper as an under bump metal (UBM) layer. The solder is applied onto this Cu UBM layer. Electroplated Cu UBM layers with thickness between 5 and 8 microns are commonly employed in the fabrication of lead-tin solder bumps for flip-chip applications. The Cu UBM provides a foundation for the solder to adhere to upon reflow and serves the function of a barrier layer between the solder and the bond pad of the IC to prevent in-diffusion of the solder into the semiconductor chip.
However, at the melting point temperature for the lead-tin solder there typically forms a tin-copper intermetallic compound which, although necessary for a reliable mechanical joint, is also brittle and prone to fracture particularly when the layer is too thick. It is therefore desirable to limit the thickness of the intermetallic layer, which can grow to become significant after multiple reflow cycles or if the bump is kept near the melting point of solder for an extended period of time. The rapid formation of the intermetallic layer is due mainly to the property of the dissolution rate of copper into tin which, in the case of eutectic lead-tin solder, constitutes 63% (by weight) of the alloy. This problem is not as important for the case of high-lead bumps with compositions of 3% or 5% tin, but becomes more severe with increased tin content. A variety of materials have been considered for use as barrier materials.
Nickel is particularly attractive for use as a barrier to the formation of a thick tin-copper (Sn6Cu5) intermetallic layer since it dissolves a factor of 25 times slower than copper (at the normal eutectic solder reflow temperature of 250xc2x0 C.). Palladium is also attractive, although less so because of its high cost.
The use of such a barrier metal is disclosed in U.S. Pat. No. 5,937,320 assigned to International Business Machines Corp, where a barrier layer comprising nickel is applied by electroplating to the UBM, here referred to as ball-limiting metallurgy. The method involves over-etching the Cu UBM beneath a thin nickel layer so as to prevent contact between the solder and exposed sides of the Cu UBM which if left in contact with the solder would cause the Cu to leach and form a thick intermetallic Snxe2x80x94Cu layer. Although this barrier layer is effective in reducing dissolution of the Cu in the solder, the disclosed fabrication technique and resultant structure suffers problems of reliability, particularly at the edge regions of the barrier, where the Cu is still able to form intermetallics.
The present invention is directed to an improved technique for forming such a barrier layer.
According to a first aspect the invention resides in a wafer having solder bumps thereon comprising a semiconductor substrate formed with metal bond pads at selected locations thereon, a metal electroplating buss layer or layers over the bond pads, a layer of solder-wettable metal on the buss layer, a layer of barrier metal which overlies and encapsulates the solder-wettable metal, and a solder bump formed on said barrier metal.
The barrier metal is preferably nickel, but may also be palladium.
The barrier metal layer may be of thickness between 0.5 and 10 microns, more preferably 1 to 3 microns.
A method of fabrication of solder bumps on a semiconductor wafer provided with metal bond pads comprises the steps of: (a) applying a metal plating buss layer over at least the bond pads; (b) forming a layer of a resist in a predefined pattern defining openings therein over said bond pads; (c) applying a layer of solder-wettable metal into said openings over the metal plating buss layer; (d) removing a volume of resist from the regions of the openings to create an opening between an edge of the layer of wettable metal and the resist; (e) applying a layer of a barrier metal over the layer of solder-wettable metal including said openings created at step (d) which encapsulates the layer of wettable metal; (f) fabricating a solder bump onto the layer of barrier metal; (g) removing the resist material; and (i) removing any exposed metal plating buss layer.
This technique allows a barrier metal cap to be readily formed, and without additional intermediate masking steps being required.
In a preferred technique the resist is removed by plasma etching, such as oxygen plasma etching. Other etching techniques such as ion beam or a reactive ion etch can be utilised.
In another preferred technique the resist is removed by chemical means. Where the resist is a photoresist as is commonly employed the chemical means may be the developer with an over-development of the existing resist employed to create the desired clearance.
The layer solder wettable under bump metal is preferably copper, and the metal plating buss layer preferably of chromium or copper-chromium alloy which enhances the adhesion and reliability of the under bump metal. This under bump metal is preferably of thickness from 1 to 10 microns, more preferably from 5 to 6 microns.
In a further aspect a method of fabrication of solder bump interconnections on a semiconductor wafer provided with metal bond pads thereon at positions where electrical connection is to be made and a passivation layer having openings over the bond pads, comprises the steps of: (a) applying a layer or layers of a metal selected from the group comprising Cr, Cr:Cu alloy, Ti, Ti:W alloy, Ni:V alloy, Cu, Ni and Au or alloys thereof; (b) applying a layer of photoresist, exposing in a desired pattern and developing to remove photoresist; from regions to leave openings in the desired pattern above said bond pads; (c) applying a layer of copper within said openings; (d) removing additional resist from at least the periphery of the openings by employing an oxygen plasma etch to create a clearance between edges of the copper layer and the remaining photoresist; (e) applying a nickel layer to form a cap over the copper layer including the sides of the layer; (f) fabricating a solder bump on the nickel layer; (g) removing the photoresist; (h) removing the layer or layers applied at step (a) from the wafer, aside from where these underlie the solder bumps; and (i) heating the wafer to cause reflow of the solder bumps.
In a still further aspect a method of fabrication of solder bump interconnections on a semiconductor wafer provided with metal bond pads thereon at positions where electrical connection is to be made and a passivation layer having openings over the bond pads, comprises the steps of: (a) applying a layer or layers of a metal selected from the group comprising Cr, Cr:Cu alloy, Ti, Ti:W alloy, Ni:V alloy, Cu, Ni and Au or alloys thereof; (b) applying a layer of photoresist, exposing in a desired pattern and developing to remove photoresist from regions to leave openings in the desired pattern above said bond pads; (c) applying a layer of copper within said openings; (d) removing additional resist from at least the periphery of the openings by further developing the exposed photoresist to create a clearance between the edges of the copper layer and the remaining photoresist; (e) applying a nickel layer to form a cap over the copper layer including the sides of the layer; (f) fabricating a solder bump on the nickel layer; (g) removing the photoresist; (h) removing the layer or layers applied at step (a) from the wafer, aside from where these underlie the solder bumps; and (i) heating the wafer to cause reflow of the solder bumps.